Beginner of FPGA.
Currently, we are creating a lock-in detection circuit using FPGA.
Device used: ATS9626 from AlazarTech
Onboard FPGA: Altera (now Intel) Stratix III
Development environment: Quartus II v13.0
The target signal to be detected is modulated at about 10MHz. For demodulation, it takes in a TTL signal having the same frequency as the modulation frequency from outside and creates an in-phase component and a quadrature component. In the prior literature (below), the TTL signal is divided into two at this time, and one of the two is differentiated to create two signals that are 90 degrees out of phase. Such a differentiation circuit is a digital circuit. So how should it be implemented?
Or is a differentiation circuit provided by Altera (Intel) IP Core?
If i have any knowledge about signal processing, FPGA, digital circuits, etc., thank you.
Reference literature: https://www.ncbi.nlm.nih.gov/pmc/articles/PMC4385102/
Answer # 1
Skip the reference
Generate a rectangular wave by expanding the reference signal (1 bit width) to an appropriate bit width.
The generated rectangular wave is passed through a bandpass IIR filter having an approximate modulation frequency as a center to obtain an in-phase component.
The quadrature component is obtained by differentiating the in-phase (subtracting 1 clock delay of in-phase and in-phase).
And very importantly, if theoretical verification is suddenly done with FPGA
Experimenting with logic synthesis one by one, the time will die.
First in Matlab, Scilab, C or Python
Anyway, let's implement it after verifying that the algorithm is correct by simulating with PC.
Answer # 2
It looks like a laboratory issue because of the atmosphere. I'll give you a hint.
I don't use the IP core when I want to process differentiation.
It's easy to understand by going back to the definition of differentiation
The difference between signals sampled at regular intervals is the differentiation.
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